The present disclosure relates to memory cell circuits, and more specifically, to enhanced temperature compensation for resistive memory cell circuits.
A prominent example for resistive memory cells having a plurality of programmable levels or states is Resistive Random Access Memory (RRAM), and more particularly, Phase Change Memory (PCM). PCM is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of specific chalcogenides between certain states of different electrical conductivity.
PCM is a non-volatile memory technology having low latency, high endurance, long retention and high scalability. PCM may utilize multi-level cell functionality to accomplish a low cost per bit, high-speed read/write operations, and high bandwidth and high endurance. Multilevel functionality (for example, multiple bits per PCM cell) may be a way to increase storage capacity and thereby to reduce cost.
Multi-level PCM may store multiple resistance levels between a lowest (SET) and a highest (RESET) resistance value at each memory cell. Multiple resistance levels (described hereafter as “levels”) correspond to partial-amorphous and partial-crystalline phase distributions of the PCM cell. Phase transformation (such as, for example, memory programming) may be enabled by Joule heating. In this regard, Joule heating can be controlled by a programming current or voltage pulse. For example, the multiple states or levels in a PCM cell may be created by varying the programming power, thus creating different crystalline and amorphous fractions within the memory cell. In metal-oxide resistive memory devices, multiple states may correspond to variations in the gap between conductive oxygen-vacancy filaments and the electrodes.
In resistive memory, the fundamental storage unit (referred to generally herein as the “cell”) can be set to a number of different states which exhibit different electrical resistance characteristics. Information may be recorded in the cells by exploiting the different material states to represent different data values. For example, to read recorded data, cell-state can be detected via measurements that exploit the differing resistance characteristics in order to differentiate between possible cell-states. Some semiconductor memory technologies may employ these basic principles for data storage, including oxide-based memory techniques using resistive RAM and memristor memory, ionic-transport-based memory, and phase-change memory.
Phase-change memory exploits the reversible switching of certain chalcogenide materials between at least two states with different electrical resistance. In single-level cell (SLC) PCM devices, each cell can be set to one of two states, crystalline and amorphous, by application of heat. Each SLC cell can thus store one bit of binary information. Storage of more than one bit per cell may be advantageous. A cell can be set to m states where m>2, and these states can be distinguished on readback via the cell resistance characteristics. In some aspects, multi-level cells (MLCs) can be set to one of m>2 resistance levels, each corresponding to a different cell state. MLC operation is achieved by exploiting partially-amorphous states of the chalcogenide cell. Different cell states can be set by varying the effective volume of the amorphous phase within the chalcogenide material. This in turn varies cell resistance.
To write data to a PCM cell, a PCM memory system may apply a voltage or current pulse to the cell to heat the chalcogenide material to an appropriate temperature to induce the desired cell-state on cooling. By varying the amplitude of the voltage or current pulses, different cell-states can be achieved. PCM memory systems may read a value at each PCM cell using cell resistance to distinguish the different cell-states. The PCM system may measure resistance for a read operation in the sub-threshold region of the current-versus-voltage (I-V) characteristic of the cell, e.g., in the region below the threshold switching voltage at which a change in cell-state can occur. A PCM system may read measurement in a variety of ways, but most techniques rely fundamentally on either voltage biasing and current sensing, or current biasing and voltage sensing. In a simple implementation of the current-sensing approach, the PCM system may bias the cell at a certain constant voltage level and sense the resulting cell current to provide a current-based metric for cell-state. PCM systems may read an output of the cell state by measuring the cell current at a known voltage. Said in other way, using conventional methods the PCM system may read the cell output by measuring a current through the cell. This solution works fine as long as one is only interested in distinguishing among a few levels that may be widely separated.
Reading MLC cells can be particularly challenging because the read operation can involve distinguishing fine differences in cell resistance via the current/voltage measurements. For example, resistance may drift to a higher resistance level with the passing of time. Resistance drift is a characteristic phenomenon observed in phase-change memory cells, which manifests itself as a steady increase in the electrical resistance of the stored cell-state over time. Drift can adversely affect the reliability of MLC storage in PCM, because the distance between adjacent levels is small and stochastic fluctuations of the resistance may be more likely to cause level overlap over time than in binary storage. Compared to SLC operation, these fine differences may be more affected by random noise fluctuations and the resistance drift, resulting in errors when retrieving stored data. To counteract this loss of data integrity associated with MLC memory, enhanced cell-state metrics can be used to compensate for the loss of data integrity.
One such used enhanced metric focuses on the sub-threshold slope of the I/V characteristic of the cell. Using this method the metric can be based on the difference between two read measurements of the same cell. This type of metric may be less sensitive to noise and drift. The metric can be a voltage based metric in the sense that it calls for the measurement of cell voltages (or cell voltage differences) at given bias currents. In general, voltage-based metrics may be advantageous over current-based metrics because the voltage-based metrics can result in less resistance drift over time, less susceptibility to noise, better SNR (signal-to-noise ratio), and may allow more intermediate levels to be packed into one cell.
However, the conventional techniques for obtaining voltage-based metrics (using current biasing and voltage sensing) may be undesirably slow. Since PCM devices may store multiple bits of information per cell, the distinguished levels may be tightly spaced. Voltage-based metrics are often used in order to pack more levels per cell, and provide more reliable readings for tightly-spaced levels. From a circuit-level perspective the standard solution of biasing the cells at a constant current and digitalizing the measured voltage may carry with it a significant cost in processing speed. This speed penalty associated with the conventional voltage measurement technique means that there may be a fundamental conflict between the requirement for a fast random access of the memory and the need for voltage-based metrics supporting high density MLC memory. For example, the hybrid approach may use a voltage-biased search loop to acquire target biasing current even though being significantly faster than other solution may not provide sufficient speed improvement to be comparable with current-based metric solutions and used in next generation of memory-based storage systems.
PCM memory is often subject to wide range of operating temperatures that can adversely affect PCM cell state readings, which are correlated to the operating temperature of the cell (even more than to the resistance drift). In addition to, each cell state may have different sensitivity to the temperature, which could provide inaccurate readouts when temperature varies. It may be advantageous to optimize voltage-based measurements for PCM cell state readings that can provide consistently accurate measurements at all operational temperatures.